===================== GPCIe Development Kit ===================== GPCIe is a PCI Express IP core developed by K&F Computing Research Co. It provides a simple interface to the backend logic designed by the user. Combining GPCIe with the backend logic, the user can easily implement an interface to other PCI Express devices without detailed knowledge about PCI Express protocol. This package includes the following three logic designs (all logic designs are provided as VHDL sources): 1) Host Interface Bridge (HIB) at the topmost layer of GPCIe design hierarchy. It provides a simple interface to the backend logic designed by the user. 2) GPCIe core, which implements the Transaction layer, the Data Link layer, and the PHY MAC sub layer defined by the PCI Express Specification, as well as the "Application layer" built over these three layers. PCI configuration registers and DMA controllers are built in this layer. 3) PHY, which implements the PHY PCS and PHY PMA sub layers using embedded Gigabit transceiver of Altera's FPGA devices. This package also includes a reference design (i.e. a sample logic) to show usage of HIB, as well as its device driver and control library which run on Linux OS. This package contains the following items: gpciepkg/ 00readme -- This file. 00readme-j -- Japanese translation of this file. 00license -- License agreement of this package. 00license-j -- Japanese translation of 00license. doc/ -- User's guide and other documents. script/ -- Utilities to install/bakup this package. software/ -- Software to control HIB. driver/ -- A source code of the HIB device driver (for Linux). win/ -- A source code of the HIB device driver (for Windwos). hibutil/ -- A source code of the HIB control library (for Linux). win/ -- A source code of the HIB control library (for Windows). include/ -- Header files for HIB control library. lib/ -- HIB control library. sample/ -- A sample program to show usage of HIB control library. tool/ -- Utilities to manage HIB control softwares. hardware_altera/ -- GPCIe IP core and its reference design (for Altera's FPGA devices) hib.vhd -- Logic design of HIB. gpcie.vhd -- Logic design of GPCIe core. phy.vhd -- Logic design of PHY. topdesign/ -- The top levels of reference designs. synth/ -- Files used for synthesis of the reference design (.qpf, .qsf, .sdc). Makefile -- A makefile to generate hib.vhd, gpcie.vhd, and phy.vhd from VHDL source template. template/ -- VHDL source template. hardware_xilinx/ -- GPCIe IP core and its reference design (for Xilinx's FPGA devices) hib.vhd -- Logic design of HIB. gpcie.vhd -- Logic design of GPCIe core. topdesign/ -- The top levels of reference designs. synth/ -- Files used for synthesis of the reference design (.qpf, .qsf, .sdc). Makefile -- A makefile to generate hib.vhd and gpcie.vhd from VHDL source template. template/ -- VHDL source template. For usage of GPCIe, see gpciepkg/doc/userguide.pdf. Before start using this package, please read the license agreement in the document. Contact address for questions and bug reports: K&F Computing Research Co. (support@kfcr.jp) -------------------------------------------------------------------------------------------------- version date author note -------------------------------------------------------------------------------------------------- 1.4.5 20-Dec-2013 AK Fixed a bug in the training sequence, that causes link up failure on some Gen3-aware chipsets. 1.4.4 19-Apr-2013 AK Windows-7 64-bit supported. 1.4.3 08-Feb-2013 AK Usage of interrupt function added to the User's Guide. 1.4.2 07-Apr-2012 AK remote update support for Cyclone IV GX. 1.4.1 14-Jan-2012 AK backend_clk dynamical reconfiguration support for Cyclone IV GX. 1.4.0 05-Dec-2011 AK Stratix II GX Gen2 support integrated (formerly in a separate package). 1.3.3 21-Nov-2011 AK Cyclone IV GX Dev Kit (soft IP Gen1 x1/x4) supported. 1.3.2 02-Mar-2011 AK Cyclone IV GX Starter Kit (soft IP Gen1 x1) supported. 1.3.1 10-Aug-2010 AK Added a function to dynamically reconfigure backend_clk frequency (Stratix IV GX only). 1.3.0 04-Jul-2010 AK Stratix IV GX (soft IP Gen1 x1/x4/x8) supported. L0s state added to LTSSM. 1.2.0 06-Mar-2010 AK Packages for free-evaluation edition and develpment suit integrated. Directory structure changed. 1.1.1 28-Nov-2009 AK Timing charts added to the User's Guide. 1.1.0 27-Aug-2009 AK logic for external PHY chip and driver for Windows added (not included in the GPCIe free-evaluation edition). 1.0.0 03-Aug-2009 AK device driver improved (support for kernel2.6.26, support for PAT, device auto recognition). 0.9.4 26-Jun-2009 AK Wrapper for embedded Gigabit transceiver (alt2gxb) for Quartus 8.1 added. 0.9.3 28-May-2009 AK support for scramble-disabled transfer added. 0.9.2 19-May-2009 AK fixed a bug on address decoding for Express Extended Configuration Registers. support response to link-retraining request. implemented receiver detection state in LTSSM. 0.9.1 22-Feb-2009 AK lower memory-resource consumption for x1. 0.9 22-Jan-2009 AK I/O space supported. 0.8.2 14-Jan-2009 AK minor bugs fixed. area consumption reduced. 0.8.1 03-Jan-2009 AK documents updated. 0.8 17-Nov-2008 AK logic optimized to satisfy timing constraint. 0.7 09-Oct-2008 AK x1 supported. 0.6 28-Sep-2008 AK DMA read function added. 0.5 28-Jul-2008 AK DMA write performance improved. English documents added. 0.1 10-Jul-2008 AK restructured. 0.0 09-Jul-2008 A. Kawai created. --------------------------------------------------------------------------------------------------