Gwrap: 

桼ѥץ饤ϩ (eg. ϥѥץ饤) FPGA ١
Υɥ󥫡ɤؼݤɬפȤʤ롢ۥȷ׻Ȥδ֤̿ 
(PCI-X, PCIe ) 󥿥եϩư륳ޥɷǤ

ʲˤơ桼ѥץ饤ϩ֥Хåɲ
ϩפȸƤӡۥȷ׻Ȥδ֤̿Ĳϩ֥󥿥ե
ϩפȸƤӤޤ


1. Gwrap ѥå

    ./00readme-j             --  Υե롣

    ./00readme               --  ΥեαѸǡ

    ./gwrap_init             -- 󥿥եϩ켰륳ޥɡ

    ./gwrap_update           -- 󥿥եϩκǾ̳ؤ򹹿륳ޥɡ

    ./ifpgagen.pl            -- 󥿥եϩκǾ̳ؤ륳ޥɡ
                                'gwrap_init'  'gwrap_update' ƤФޤ

    ./samples/               -- ХåɲϩΥץ롣

    ./samples/loopback       -- ۥȤäǡ򤽤ΤޤޥۥȤ֤ϩ
                                Хåɲϩȥ󥿥եϩƱΥåƱ
                                ưޤ

    ./samples/g5m100         -- GRAPE-7 Model100 Ѥ G5 ϩѥץ饤ϩȥ󥿥ե
                                ϩƱΥåƱưޤ

    ./samples/g5m600         -- GRAPE-7 Model600/300 Ѥ G5 ϩѥץ饤ϩȥ󥿥ե
                                ϩƱΥåƱưޤg5m100 ȤۤȤƱǤ
                                g5m600 ˤ backend_run Ȥ port Τߤۤʤޤ

    ./samples/g5m100dualclk  -- GRAPE-7 Model100 Ѥ G5 ϩѥץ饤ϩȥ󥿥ե
                                ϩ̸ĤΥåƱưޤ


2. Gwrap ޥɤλˡ

  (1) gwrap.tar.gz Ÿ gwrap Ȥǥ쥯ȥ꤬Ǥޤ
      ǥ쥯ȥΥեѥ̾Ķѿ GWRAPPATH ꤷƲ

        ex) setenv GWRAPPATH $HOME/src/gwrap

  (2) Ŭʥǥ쥯ȥˡΥХåɲϩѰդޤХå
      ɲϩΥץ뤬 $GWRAPPATH/samples/ ѰդƤޤ
      ϤƻѤˤϤΥץѤ gwrap ư
      򡦳ǧ뤳Ȥᤷޤ

      Хåɲϩ entity ΥեޥåȤˤĤƤ 3. Хå
      ɲϩ entityפ򻲾ȤƤ

  (3) Хåɲϩ֤ǥ쥯ȥ꤫ $GWRAPPATH/gwrap_init 
      ޥɤ¹Ԥޤgwrap_init ϰ 2 ĤȤޤ1 ܤ
      ϡɥΥƥ㡢2 ܤϥХåɲϩκǾ̳
      ؤҤƤ VHDL եΥե̾ǤʳǤϰʲ
       10 Υƥ򥵥ݡȤƤޤ

            dr3:     GRAPE-DR TB3 (preliminary)   PCIe x4       125MHz
            g7m1:    KFCR GRAPE-7 model100        PCI-X         133MHz
            g7p1:    KFCR GRAPE-7 model300/600    pFPGA1,4      100MHz
            g7p2:    KFCR GRAPE-7 model300/600    pFPGA2,3,5    100MHz
            g7p6:    KFCR GRAPE-7 model300/600    pFPGA6        100MHz
            dkx4:    PLDA DesignKit               PCIe x4       125MHz
            gx2x4:   PLDA XpressGX2               PCIe x4       125MHz
            gx2x4f:  PLDA XpressGX2               PCIe x4       125MHz, fully licensed core
            gx2x8:   PLDA XpressGX2               PCIe x8       250MHz
            gx2x8f:  PLDA XpressGX2               PCIe x8       250MHz, fully licensed core

          ex1)
              cp -r $GWRAPPATH/samples/g5m100 ./testifpga
              cd testifpga
              $GWRAPPATH/gwrap_init g7m1 pg_proc.vhd

          ex1 ϥǥ쥯ȥ testifpga  model100 ѤΥ󥿥ե
          ϩޤQuartusII  ifpga.qpf 򳫤ѥ
          뤹ȡifpga.sof Ǥޤ

          ex2)
              cp -r $GWRAPPATH/samples/g5m600 ./testpfpga
              cd testpfpga
              $GWRAPPATH/gwrap_init g7p1 pg_proc.vhd

          ex2 ϥǥ쥯ȥ testpfpga  model600 pFPGA1 ѥ󥿥ե
          ϩޤQuartusII  pfpga3.qpf 򳫤ѥ
          뤹ȡpfpga3.sof  pfpga3.ttf Ǥޤ

          ex3)
              cd testpfpga
              $GWRAPPATH/gwrap_init g7m1 my_backend.vhd

          ex3 ϥǥ쥯ȥ testpfpga  model100 ѤΥ󥿥ե
          ϩޤ testpfpga ˤϥ桼κ
          Хåɲϩ餫ѰդƤꡢκǾ̳ؤ 
          my_backend.vhd ˵ҤƤΤȤޤQuartusII  
          ifpga.qpf 򳫤ѥ뤹ȡifpga.sof Ǥ
          κ QuartusII ϡ桼κХåɲϩ
          ޤ VHDL ե뤫ɬפʵҤưŪõФƥѥ
          Ѥޤɬפʥե̾򤢤餫 ifpga.qsf 
          ˼ưɲäƤۤμ¤Ǥ


      ƥ (ɤΥԥ֤ FPGAIP corephy) ˰¸
      եΥƥץ졼ȤϤ٤ƥǥ쥯ȥ $GWRAPPATH ˤ
      ޤ$GWRAPPATH/gwrap_init ¹Ԥȡ饢ƥ
      ˱ե뤬򤵤졢ȥǥ쥯ȥ˥ԡޤ
      ޤ桼λꤷХåɥեƤ 
      backend entity  port ˱ top  (ifpga.vhd ޤ 
      pfpga3.vhd) ޤ $GWRAPPATH/ifpgagen.pl Ԥ
      ޤ

      ƥ˰¸ե (.qsf Ƽ Wizard 
      ե) ѹˤϡ$GWRAPPATH ΥեԽ
       gwrap_init ¹Ԥޤ桼ǥ쥯ȥˤե
      ԽƤ⡢gwrap_init ¹ԤȾ񤭤Ƥޤޤ

  (4) backend entity  port ѹäˤϡ
      $GWRAPPATH/gwrap_update ¹ԤȡȿǤ褦 top 
      ؤβϩʤޤ (¸ top ؤϴ˾񤭤
      ޤ)gwrap_update ΰ gwrap_init ΤƱǤ


3. Хåɲϩ entity

ХåɲϩǾ̳ entity ̾ backend ǤʤƤϤʤޤ
gwrap_init  gwrap_update  2 ˤϡ entity Ҥ
Ƥ VHDL ե̾Ϳޤ

backend entity ϰʲ I/O port ޤ

entity backend is
  port (
    -- DMA signals
    hib_we             : in std_logic;                      -- write enable from the interface logic
    hib_data           : in std_logic_vector(63 downto 0);  -- data from the interface logic
    backend_we         : out std_logic;                     -- write enable to the interface logic
    backend_data       : out std_logic_vector(63 downto 0); -- data to the interface logic

    -- board info register initial value
    board_info         : out std_logic_vector(31 downto 0); -- board ID tag

    -- global signals
    hib_clk            : in std_logic;    -- interface clock
    backend_clk0       : in std_logic;    -- backend clock (optional)
    backend_clk1       : in std_logic;    -- backend clock (optional)
    backend_clk2       : in std_logic;    -- backend clock (optional)

    rst: in std_logic                     -- reset (negative logic)
    );
end backend;

Τ backend_clk[012] ٤Ƥ port ɬܤǤ

board_info ѤʤˤϡνϤˤŬͤꤷƤ
  eg. board_info <= conv_std_logic_vector(0, 32);

backend_clk[012] ɬפ˱ƵҤޤbackend_clk[012] Υå
ȿ QuartusII MegaWizard  ifpgapll.vhd 򳫤ꤷޤ
ͤ PCI-X interface ξ 133MHz, PCIe interface ξ 125MHz 
Ǥ

Хåɲϩ FPGA ȤĤʤɬפʾˤϡbackend
entity  port ʸǤդξɵǤޤɵϡϩ
Ǿ̳ (ifpga.vhd)  port ̤ FPGA ؼưŪ˷ޤ


4. 

  --------------------------------------------------------------------------------------------------
  version       date        author               note
  --------------------------------------------------------------------------------------------------
   0.6          17-Dec-2007 AK                   support for arch 'g7m8'.

   0.5          20-Jul-2007 AK                   optional backend clock added.
                                                 'loopback' sample logic added.

   0.4          19-Jul-2007 AK                   support for arch 'dr3'

   0.3          13-Jul-2007 AK                   support for arch 'gx2x8a'.
                                                 '00readme' and 'Makefile' added.

   0.2          31-May-2007 AK                   support for arch 'g7p[126]a'.

   0.1          12-May-2007 AK                   support for arch 'g7p[126]'.

   0.0          09-May-2007 Atsushi Kawai        created.
  --------------------------------------------------------------------------------------------------

䤤碌ӥХݡȤϲؤꤤޤ:
K&F Computing Research (support@kfcr.jp)
