Products : GRAPE-9 : Acceleration System for Scientific Simulation
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| GRAPE-9 model5000/8. Eight processor cards installed. |
The processor card (parts side). |
The processor card (solder side). |
Key Features
- Houses hardwired pipelines dedicated to a given scientific simulation.
- Processes arithmetic operations not by a software program but by
a hardware logic, realizing excellent Gflops per Watt values, e.g., in
some applications, it shows 4 times higher Gflops/W value than NVIDIA
GTX Titan.
- Offers close-to-peak performance even at lower degrees of
parallelism ( < 1000). Therefore, paritcle simulations of
protoplanetary systems and globular clusters, for example, can be
performed at reasonable speed, even with a rather small number of
particles ( < 10k).
- A user library provides APIs to handle the processor chips. From
the point of view of the user, all processor chips can be handled as a
single device, and thus, the user does not need to write a parallel
code in order to make the chips run in parallel.
- The pipeline logics are integrated into 16 processor chips (Altera's FPGA).
The logics are reconfigurable.
- Two pipeline logics for gravitational force calculation
(equivalent to GRAPE-5 and GRAPE-6) are bundled. The user library
provides APIs compatible with conventional GRAPEs including GRAPE-5,
GRAPE-6 and GRAPE-DR. Users of these hardwares can seamlessly migrate
their own application codes.
- Users can design their own pipelines with a pipeline-designing
utility PGPG2note1.
Technical Specifications
| Processor chip |
Altera CycloneV GX (5CGXFC9) x 16 |
| Host interface |
Gen2 16-lane PCI Express (2 hoses at maximum configuration).
Each processor chip is connected to a switch device (PEX8696) via Gen1 4-lane PCI Express,
and it can transparently be accessed from the host as an independent PCI Express device.
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| Pre-installed pipeline logic: |
Gravity interaction (GRAPE-6 equivalent), about 3 Tflops peak (preliminary)
Gravity interaction (GRAPE-5 equivalent), about 12 Tflops peak (preliminary)
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| On-board memory |
16 GB (1GB DDR2 memory on each processor card). |
| Power supply |
100-220V AC |
| Power consumption (approx. max) |
300 W |
| Miscellaneous |
- Processor cards are installed in a chassis with a power
supply unit and cooling fans. The chassis is connected
to the host computer via Gen2 16-lane PCI Express
External Cable.
- The device driver and data-transfer library handle each
processor chip as an independent PCI device. The user
library provides APIs to handle all the chips as a signle
device. Also, it provides APIs to handle each chip as an
independent device.
- The pipeline logics of the processor chips can be reconfigured from the host computer.
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Softwares, Data, and Documents
- GRAPE Software Package : Basic
softwares including a device driver, and GRAPE-5/6/7/DR compatible
libraries for gravitational-force calculation.
- Pipeline-Designing Utility PGPG2 (Optional) :
A software utility with which users can develop their own pipeline logics.
Measured Performance
In preparation.
International Price
- GRAPE-9 model5000 (16 processor chips) : 2,688,000 JPY
- GRAPE-9 model5000/8 (8 processor chips) : 1,344,000 JPY
Initial technical support for 2 years.
A GRAPE-9 system shipped with the host computer, cooling fans and
software enviroments. The overall system is completely set up and
thoroughly checked in our company before shipping. The system (CPU,
chipset, memory size, disk size, chassis) can be customized so that it
would suit your requirement. Please contact info@kfcr.jp for detail.
PGPG2 (Pipeline Generator for Programmable GRAPE, generation 2note1) is a pipeline-designing utility, with which
users can describe arithmetic computations using a high-level language
similar to C. The utility converts the description into a pipeline
logic for GRAPE-9. Also it generates a user library to handle the logic.
- Converts a pipeline design described in a high level language, PG2,
into a hardware logic described in VHDL. Typically, a 10 to 100 lines
of description in PG2 is converted into a 1,000 to
10,000 lines of description in VHDL.
- A pipeline logic generated by the utility is combined with an
interface logicnote2 (a logic that control
data transfer between GRAPE-9 and the host), so that it can be
synthesized using Altera's Quartus II. FPGA devices (i.e, processor
chips) on a GRAPE-9 can be configured with the synthesized logic.
- A user library and its header file to handle the pipeline from
the host computer are also generated.
Copyright
Copyright of the following items belong to K&F Computing Research
Co. (hereafter KFCR).
- The product itself.
- VHDL source code, netlist and bitstream data generated by the productnote2.
License Agreement
- VHDL source code, netlist generated by the product and the product itself must be used only with GRAPE-9.
Modification intended for use on other hadware platforms is prohibited.
- Distribution of VHDL source code, netlist generated by the product and the product itself are prohibited,
unless the end user is a legal user of the product.
- Duplication of the product is permitted as long as it is used by legal users.
There is no limitation on the number of duplications.
- Bitstream data (e.g., SOF files and POF files) generated using the product
can be distributed or sold.
Please contanct us for usage violating the above license agreement.
International Price
249,900 JPY
Includes a pipeline design description by PG2, and a pipeline logic generated from it, for any given application.
Initial technical support for 2 years.
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| GRAPE-9 model800 |
The processor card (parts side). |
The processor card (solder side). |
Key Features
- Houses hardwired pipelines dedicated to a given scientific simulation.
- Processes arithmetic operations not by a software program but by
a hardware logic, realizing excellent Gflops per Watt values, e.g., in
some applications, it shows 5 times higher Gflops/W value than NVIDIA
GTX 580.
- Offers close-to-peak performance even at lower degrees of
parallelism ( < 1000). Therefore, paritcle simulations of
protoplanetary systems and globular clusters, for example, can be
performed at reasonable speed, even with a rather small number of
particles ( < 10k).
- A user library provides APIs to handle the processor chips. From
the point of view of the user, all processor chips can be handled as a
single device, and thus, the user does not need to write a parallel
code in order to make the chips run in parallel.
- The pipeline logics are integrated into 8 processor chips (Altera's FPGA).
The logics are reconfigurable.
- Two pipeline logics for gravitational force calculation
(equivalent to GRAPE-5 and GRAPE-6) are bundled. The user library
provides APIs compatible with conventional GRAPEs including GRAPE-5,
GRAPE-6 and GRAPE-DR. Users of these hardwares can seamlessly migrate
their own application codes.
- Users can design their own pipelines with a pipeline-designing
utility PGPG21.
Technical Specifications
| Processor chip |
Altera CycloneIV GX (EP4CGX150) x 8 |
| Host interface |
Gen2 16-lane PCI Express (2 hoses at maximum configuration).
Each processor chip is connected to a switch device (PEX8696) via Gen1 4-lane PCI Express,
and it can transparently be accessed from the host as an independent PCI Express device.
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| Pre-installed pipeline logic: |
Gravity interaction (GRAPE-6 equivalent), 80 pipelines at 149MHz operation (680 Gflops peak)
Gravity interaction (GRAPE-5 equivalent), 448 pipelines at 186MHz operation (3.17 Tflops peak)
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| On-board memory |
16 GB (2GB DDR2 memory on each processor card). |
| Power supply |
100-220V AC |
| Power consumption (approx. max) |
150 W |
| Miscellaneous |
- Processor cards are installed in a chassis (100 mm x 306
mm x 402 mm) with a power supply unit and cooling fans.
The chassis is connected to the host computer via Gen2
16-lane PCI Express External Cable.
- The device driver and data-transfer library handle each
processor chip as an independent PCI device. The user
library provides APIs to handle all the chips as a signle
device. Also, it provides APIs to handle each chip as an
independent device.
- The pipeline logics of the processor chips can be reconfigured from the host computer.
|
Softwares, Data, and Documents
- GRAPE Software Package : Basic
softwares including a device driver, and GRAPE-5/6/7/DR compatible
libraries for gravitational-force calculation.
- Pipeline-Designing Utility PGPG2 (Optional) :
A software utility with which users can develop their own pipeline logics.
Measured Performance
In preparation.
International Price
840,000 JPY
Initial technical support for 2 years.
- 1: PGPG2 is a utility designed and developed
by K & F Computing Research Co. based on PGPG (Hamada et al.,
2005). There exists another extension of PGPG, named PGR (Hamada
& Nakasato, 2005). The concept of "pipeline description by a
high-level language" is proposed by Dr. Nakasato (Aizu University) in
2006.
- note2: A complete VHDL source code generated
by the product may include code snippets copied from the product itself.
- Contact: info@kfcr.jp